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pre-production this is a product in the pre-production phase of development. device ramtron international corporation characterization is complete and ramtron does not expect to change the 1850 ramtron drive, colorado springs, co 80921 specifications. ramtron will issue a product change notice if any (800) 545-fram, (719) 481-7000 specification changes are made. http://www.ramtron.com rev. 2.0 may 2010 page 1 of 16 fm24v05 512kb serial 3v f-ram memory features 512k bit ferroelectric nonvolatile ram ? organized as 65,536 x 8 bits ? high endurance 100 trillion (10 14 ) read/writes ? 10 year data retention ? nodelay? writes ? advanced high-reliability ferroelectric process fast two-wire serial interface ? up to 3.4 mhz maximum bus frequency ? direct hardware replacement for eeprom ? supports legacy timing for 100 khz & 400 khz device id and serial number ? device id reads out manufacturer id & part id ? unique serial number (fm24vn05) low voltage, low power operation ? low voltage operation 2.0v ? 3.6v ? active current < 150 a (typ. @ 100khz ) ? 90 a standby current (typ.) ? 5 a sleep mode current (typ.) industry standard configuration ? industrial temperature -40 c to +85 c ? 8-pin ?green?/rohs soic package description the fm24v05 is a 512kbit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes like a ram. it provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. the fm24v05 performs write operations at bus speed. no write delays are incurred. the next bus cycle may commence immediately without the need for data polling. in addition, the product offers write endurance orders of magnitude higher than eeprom. also, f-ram exhibits much lower power during writes than eeprom since write operations do not require an internally elevated power supply voltage for write circuits. these capabilities make the fm24v05 ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows more frequent data writing with less overhead for the system. the fm24v05 provides substantial benefits to users of serial eeprom, yet these benefits are available in a hardware drop-in replacement. the devices are available in industry standard 8-pin soic package using a familiar two-wire (i 2 c) protocol. the fm24vn05 is offered with a unique serial number that is read-only and can be used to identify a board or system. both devices incorporate a read-only device id that allows the host to determine the manufacturer, product density, and product revision. the devices are guaranteed over an industrial temperature range of -40c to +85c. pin configuration a0 a1 a2 vss vdd wp scl sda 1 2 3 4 8 7 6 5 pin name function a0-a2 device select address sda serial data/address scl serial clock wp write protect vdd supply voltage vss ground
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 2 of 16 address latch 8k x 64 fram array data latch 8 sda counter serial to parallel converter control logic scl wp a0-a2 device id and serial number 8 figure 1. fm24v05 block diagram pin description pin name type pin description a0-a2 input device select address 0-2: these pins are used to select one of up to 8 devices of the same type on the same two-wire bus. to select the device, the address value on the two pins must match the corresponding bits contained in the slave address. the address pins are pulled down internally. sda i/o serial data/address: this is a bi-directional pin for the two-wire interface. it is open-drain and is intended to be wire-or?d with other devices on the two-wire bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling edges. an external pull-up resistor is required. scl input serial clock: the serial clock pin for the two-wire interface. data is clocked out of the part on the falling edge, and into the device on the rising edge. the scl input also incorporates a schmitt trigger input for noise immunity. wp input write protect: when tied to vdd, addresses in the entire memory map will be write- protected. when wp is connected to ground, all addresses may be written. this pin is pulled down internally. vdd supply supply voltage vss supply ground
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 3 of 16 overview the fm24v05 is a family of serial f-ram memory devices. the memory array is logically organized as a 65,536 x 8 bit memory array and is accessed using an industry standard two-wire (i 2 c) interface. functional operation of the f-ram is similar to serial eeprom. the major difference between the fm24v05 and serial eeprom is f-ram?s superior write performance. memory architecture when accessing the fm24v05, the user addresses 65,536 locations each with 8 data bits. these data bits are shifted serially. the 65,536 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish other non-memory devices) and a 2-byte address. all 16 address bits are used by the decoder for accessing the memory. the access time for memory operation is essentially zero beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the two-wire bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. this is explained in more detail in the interface section below. users expect several obvious system benefits from the fm24v05 due to its fast write cycle and high endurance as compared with eeprom. however there are less obvious benefits as well. for example in a high noise environment, the fast-write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note that it is the user?s responsibility to ensure that v dd is within datasheet tolerances to prevent incorrect operation. two-wire interface the fm24v05 employs a bi-directional two-wire bus protocol using few pins or board space. figure 2 illustrates a typical system configuration using the fm24v05 in a microcontroller-based system. the industry standard two-wire bus is familiar to many users but is described in this section. by convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm24v05 always is a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions including start, stop, data bit, or acknowledge. figure 3 illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electrical specifications section. microcontroller sda scl fm24v05 a0 a1 a2 sda scl fm24v05 a0 a1 a2 vdd r min = 1.1 k ohm r max = t r/cbus figure 2. typical system configuration
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 4 of 16 stop (master) start (master) 7 data bits (transmitter) 6 0 data bit (transmitter) acknowledge (receiver) scl sda figure 3. data transfer protocol stop condition a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations using the fm24v05 should end with a stop condition. if an operation is in progress when a stop is asserted, the operation will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all commands should be preceded by a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm24v05 for a new operation. if during operation the power supply drops below the specified v dd minimum, the system should issue a start condition prior to performing another operation. data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the two conditions described above, the sda signal should not change while scl is high. acknowledge the acknowledge takes place after the 8 th data bit has been transferred in any transaction. during this state the transmitter should release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no-acknowledge and the operation is aborted. the receiver would fail to acknowledge for two distinct reasons. first is that a byte transfer fails. in this case, the no-acknowledge ceases the current operation so that the part can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowledge to deliberately end an operation. for example, during a read operation, the fm24v05 will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). when a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. if the receiver acknowledges the last byte, this will cause the fm24v05 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. slave address the first byte that the fm24v05 expects after a start condition is the slave address. as shown in figure 4, the slave address contains the device type or slave id, the device select address bits, a page address bit, and a bit that specifies if the transaction is a read or a write. bits 7-4 are the device type (slave id) and should be set to 1010b for the fm24v05. these bits allow other function types to reside on the 2-wire bus within an identical address range. bits 3-1 are the device select address bits. they must match the corresponding value on the external address pins to select the device. up to eight fm24v05 devices can reside on the same two-wire bus by assigning a different address to each. bit 0 is the read/write bit. r/w=1 indicates a read operation and r/w=0 indicates a write operation. high speed mode (hs-mode) the fm24v05 supports a 3.4mhz high speed mode. a master code (0000 1 xxx b) must be issued to place the device into high speed mode. communication between master and slave will then be enabled for speeds up to 3.4mhz. a stop condition will exit hs- mode. single- and multiple-byte reads and writes are supported. see figures 10 and 11 for hs-mode timings.
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 5 of 16 figure 4. slave address addressing overview after the fm24v05 (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. the address requires two bytes. the complete 16-bit address is latched internally. each access causes the latched address value to be incremented automatically. the current address is the value that is held in the latch -- either a newly written value or the address following the last access. the current address will be held for as long as power remains or until a new value is written. reads always use the current address. a random read address can be loaded by beginning a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm24v05 increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last address (ffffh) is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. data transfer after the address information has been transmitted, data transfer between the bus master and the fm24v05 can begin. for a read operation the fm24v05 will place 8 data bits on the bus then wait for an acknowledge from the master. if the acknowledge occurs, the fm24v05 will transfer the next sequential byte. if the acknowledge is not sent, the fm24v05 will end the read operation. for a write operation, the fm24v05 will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the fm24v05 is designed to operate in a manner very similar to other 2-wire interface memory products. the major differences result from the higher performance write capability of f-ram technology. these improvements result in some differences between the fm24v05 and a similar configuration eeprom during writes. the complete operation for both writes and reads is explained below. write operation all writes begin with a slave address, then a memory address. the bus master indicates a write operation by setting the lsb of the slave address (r/w bit) to a ?0?. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap from ffffh to 0000h. unlike other nonvolatile memory technologies, there is no effective write delay with f-ram. since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or write can occur immediately following a write. acknowledge polling, a technique used with eeproms to determine if a write is complete is unnecessary and will always return a ready condition. internally, an actual memory write occurs after the 8 th data bit is transferred. it will be complete before the acknowledge is sent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8 th data bit. the fm24v05 uses no page buffering. the memory array can be write-protected using the wp pin. this feature is available only on fm24v05 and fm24vn05 devices. setting the wp pin to a high condition (v dd ) will write-protect all addresses. the fm24v05 will not acknowledge data bytes that are written to protected addresses. in addition, the address counter will not increment if writes are attempted to these addresses. setting wp to a low state (v ss ) will deactivate this feature. wp is pulled down internally. figures 5 and 6 below illustrate a single-byte and multiple-byte write cycles. 1 010a2 r/w slave id 765 4 3 2 1 0 a1 a0 device select
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 6 of 16 s a slave address 0 address msb a data byte a p by master by fm24v05 start address & data stop acknowledge address lsb a figure 5. single byte write s a slave address 0 address msb a data byte a p by master by fm24v05 start address & data stop acknowledge address lsb a data byte a figure 6. multiple byte write read operation there are two basic types of read operations. they are current address read and selective address read. in a current address read, the fm24v05 uses the internal address latch to supply the address. in a selective read, the user performs a procedure to set the address to a specific value. current address & sequential read as mentioned above the fm24v05 uses an internal latch to supply the address for a read operation. a current address read uses the existing value in the address latch as a starting place for the read operation. the system reads from the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to a ?1?. this indicates that a read operation is requested. after receiving the complete slave address, the fm24v05 will begin shifting out data from the current address on the next clock. the current address is the value held in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. each time the bus master acknowledges a byte, this indicates that the fm24v05 should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus contention as the fm24v05 attempts to read out additional data onto the bus. the four valid methods are: 1. the bus master issues a no-acknowledge in the 9 th clock cycle and a stop in the 10 th clock cycle. this is illustrated in the diagrams below. this is preferred. 2. the bus master issues a no-acknowledge in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. 4. the bus master issues a start in the 9 th clock cycle. if the internal address reaches ffffh, it will wrap around to 0000h on the next read cycle. figures 7 and 8 below show the proper operation for current address reads. selective (random) read there is a simple technique that allows a user to select a random address location as the starting point for a read operation. this involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb set to 0. this specifies a write operation. according to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. after the fm24v05 acknowledges the address, the bus master
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 7 of 16 issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address lsb set to a ?1?. the operation is now a current address read. s a slave address 1 data byte 1 p by master by fm24v05 start address stop acknowledge no acknowledge data figure 7. current address read s a slave address 1 data byte 1 p by master by fm24v05 start address stop acknowledge no acknowledge data data byte a acknowledge figure 8. sequential read s a slave address 1 data byte 1 p by master by fm24v05 start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a figure 9. selective (random) read s a slave address 1 data byte 1 p by master by fm24v05 start & enter hs-mode address stop & exit hs-mode no acknowledge data s 1 start acknowledge x x x 1 0 0 0 0 hs-mode command no acknowledge figure 10. hs-mode current address read s a slave address 0 data byte a p by master by fm24v05 start & enter hs-mode address & data stop & exit hs-mode s 1 start acknowledge x x x 1 0 0 0 0 hs-mode command address msb a address lsb a no acknowledge figure 11. hs-mode byte write
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 8 of 16 sleep mode a low power mode called sleep mode is implemented on both fm24v05 and fm24vn05 devices. the device will enter this low power state when the sleep command 86h is clocked-in. sleep mode entry can be entered as follows: 1. the master sends a start command. 2. the master sends reserved slave id 0xf8 3. the master sends the i 2 c-bus slave address of the slave device it needs to identify. the last bit is a ?don?t care? value (r/w bit). only one device must acknowledge this byte (the one that has the i 2 c-bus slave address). 4. the master sends a re-start command. 5. the master sends reserved slave id 0x86 6. the fm24v05 sends an ack. 7. the master sends stop to ensure the device enters sleep mode. once in sleep mode, the device draws i zz current, but the device continues to monitor the i 2 c pins. once the master sends a slave address that the fm24v05 identifies, it will ?wakeup? and be ready for normal operation within t rec (400 s max.). as an alternative method of determining when the device is ready, the master can send read or write commands and look for an ack. while the device is waking up, it will nack the master until it is ready. s a p by master by fm24v05 start address stop s a rsvd slave id (f8) slave address a start address acknowledge rsvd slave id (86) x figure 12. sleep mode entry
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 9 of 16 device id the fm24v05 and fm24vn05 devices incorporate a means of identifying the device by providing three bytes of data, which are manufacturer, product id, and die revision. the device id is read-only. it can be accessed as follows: 1. the master sends a start command. 2. the master sends reserved slave id 0xf8 3. the master sends the i 2 c-bus slave address of the slave device it needs to identify. the last bit is a ?don?t care? value (r/w bit). only one device must acknowledge this byte (the one that has the i 2 c-bus slave address). 4. the master sends a re-start command. 5. the master sends reserved slave id 0xf9 6. the device id read can be done, starting with the 12 manufacturer bits, followed by the 9 part identification bits, and then the 3 die revision bits. 7. the master ends the device id read sequence by nacking the last byte, thus resetting the slave device state machine and allowing the master to send the stop command. note: the reading of the device id can be stopped anytime by sending a nack command. s a data byte data byte 1 p by master by fm24v05 start address stop no acknowledge data s a rsvd slave id (f8) slave address a start address acknowledge rsvd slave id (f9) a a data byte acknowledge figure 13. read device id manufacturer id product id die rev. 11 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 2 1 0 ramtron density variation 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 n 0 0 0 0 0 0 0 figure 14. manufacturer and product id density: 01h=128kb, 02h=256kb, 03h=512kb, 04=1mb variation: product id bit 4 = s/n, product id bit 0 = reserved the 3-byte hex code for an fm24v05 will be: 0x00 0x43 0x00 the 3-byte hex code for an fm24vn05 will be: 0x00 0x43 0x80
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 10 of 16 unique serial number (fm24vn05 only) the fm24vn05 device also incorporates a read-only 8-byte serial number. it can be used to uniquely identify a pc board or system. the serial number includes a 40-bit unique number, an 8-bit crc, and a 16-bit number that can be defined upon request by the customer. if a customer-specific number is not requested, the 16-bit customer identifier is 0x0000. the 8 bytes of data are accessed via a slave address sequence similar to the device id. the serial number can be read by the system as follows: 1. the master sends a start command 2. the master sends reserved slave id 0xf8 3. the master sends the i 2 c-bus slave address of the slave device it needs to identify. the last two bits are ?don?t care? values. only one device must acknowledge this byte (the one that has the i 2 c-bus slave address). 4. the master sends a re-start command 5. the master sends reserved slave id 0xcd to read the serial number. 6. the master ends the serial number read sequence by nacking the last byte, thus resetting the slave device state machine and allowing the master to send the stop command. the 8-bit crc value can be used to compare to the value calculated by the controller. if the two values match, then the communication between slave and master was performed without errors. the function (shown below) is used to calculate the crc value. to perform the calculation, 7 bytes of data are filled into a memory buffer in the same order as they are read from the part ? i.e. byte7, byte6, byte5, byte4, byte3, byte2, byte1 of the serial number. the calculation is performed on the 7 bytes, and the result should match the final byte out from the part which is byte0, the 8-bit crc value. customer identifier * 40-bit unique number 8-bit crc sn(63:56) sn(55:48) sn(47:40) sn(39:32) sn(31:24) sn(23:16) sn(15:8) sn(7:0) * contact factory for requesting a customer identifier number. figure 15. 8-byte serial number (read-only) s a data byte 7 1 p by master by fm24vn05 start address stop no acknowledge data s a rsvd slave id (f8) slave address a start address acknowledge rsvd slave id (cd) a a data byte 0 acknowledge figure 16. read serial number function to calculate crc byte calccrc8( byte* pdata, int nbytes ) { static byte crctable[256] = { 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd, 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea, 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a, 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0d, 0x0a, 0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42,
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 11 of 16 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a, 0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4, 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4, 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44, 0x19, 0x1e, 0x17, 0x10, 0x05, 0x02, 0x0b, 0x0c, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34, 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63, 0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x06, 0x01, 0x08, 0x0f, 0x1a, 0x1d, 0x14, 0x13, 0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83, 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3 }; byte crc = 0; while( nbytes-- ) crc = crctable[crc ^ *pdata++]; return crc; }
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 12 of 16 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +4.5v v in voltage on any pin with respect to v ss -1.0v to +4.5v and v in < v dd +1.0v * t stg storage temperature -55 c to +125 c t lead lead temperature (soldering, 10 seconds) 260 c v esd electrostatic discharge voltage - human body model (aec-q100-002 rev. e) - charged device model (aec-q100-011 rev. b) - machine model (aec-q100-003 rev. e) 2.5kv 1.25kv 200v package moisture sensitivity level msl-1 * exception: the ?v in < v dd +1.0v? restriction does not apply to the scl and sda inputs. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions (t a = -40 c to + 85 c, v dd =2.0v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd main power supply 2.0 3.3 3.6 v i dd v dd supply current @ scl = 100 khz @ scl = 1 mhz @ scl = 3.4 mhz 175 400 1000 a a a 1 i sb standby current 90 150 a 2 i li input leakage current 1 2.7v) 0.4 v v ol2 output low voltage ( i ol = 150 a) 0.2 v r in address input resistance (wp, a2-a0) for v in = v il (max) for v in = v ih (min) 50 1 k ? m ? 4 notes 1. scl toggling between v dd -0.2v and v ss , other inputs v ss or v dd -0.2v. 2. scl = sda = v dd . all inputs v ss or v dd . stop command issued. 3. vin or vout = v ss to v dd . does not apply to wp, a2-a0 pins. 4. the input pull-down circuit is stronger (50k ? ) when the input voltage is below v il and weak (1m ? ) when the input voltage is above v ih .
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 13 of 16 ac parameters (t a = -40 c to + 85 c, v dd =2.0v to 3.6v unless otherwise specified) f/s-mode (c l <500pf) hs-mode (c l <100pf) symbol parameter min max min max units notes f scl scl clock frequency 0 1.0 0 3.4 mhz 1 t low clock low period 500 160 ns t high clock high period 260 60 ns t aa scl low to sda data out valid 450 130 ns t buf bus free before new transmission 0.5 0.3 notes: all scl specifications as well as start and stop conditions apply to both read and write operations. 1. the speed-related specifications are guaranteed characteristic points along a continuous curve of operation from dc to f scl (max). 2. this parameter is periodically sampled and not 100% tested. 3. in hs-mode and v dd < 2.7v, the t su:dat (min.) spec is 15ns. capacitance (t a = 25 c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c i/o input/output capacitance (sda) - 8 pf 1 c in input capacitance - 6 pf 1 notes 1. this parameter is periodically sampled and not 100% tested. power cycle timing (t a = -40 c to +85 c, v dd = 2.0v to 3.6v) symbol parameter min max units notes t vr v dd rise time 50 - s/v 1,2 t vf v dd fall time 100 - s t pd last access (stop condition) to power down (v dd min) 0 - s t rec recovery time from sleep mode - 400 s notes 1. this parameter is characterized and not 100% tested. 2. slope measured at any point on v dd waveform. power cycle timing
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 14 of 16 ac test conditions equivalent ac test load circuit input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagram notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters apply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant datasheet sections. these diagrams illustrate the timing parameters only. read bus timing t su:sda start t r ` t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:dat t aa t dh scl sda write bus timing t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda data retention (t a = -40 c to +85 c) parameter min max units notes data retention 10 - years 3.6v output 1.8 k ohm 100 pf
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 15 of 16 mechanical drawing 8-pin soic (jedec standard ms-012 variation aa) refer to jedec ms-012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxxx= part number, p=package type r=rev code, lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm24v05, ?green?/rohs soic package, rev. a, lot 9646447, year 2010, work week 11 without s/n feature with s/n feature fm24v05-g fm24vn05-g a9646447 a9646447 ric1011 ric1011 xxxxxx-p rlllllll ricyyww
fm24v05 - 512kb i2c fram rev. 2.0 may 2010 page 16 of 16 revision history revision date summary 1.0 8/22/2008 initial release 1.1 2/2/2009 added tape and reel ordering information. 2.0 5/25/2010 changed to pre-production status. updated esd ratings. changed part marking scheme. expanded crc check description. ordering information part number features operating voltage package fm24v05-g device id 2.0-3.6v 8-pin ?green?/rohs soic fm24vn05-g device id, s/n 2.0-3.6v 8-pin ?green?/rohs soic fm24v05-gtr device id 2.0-3.6v 8-pin ?green?/rohs soic, tape & reel fm24vn05-gtr device id, s/n 2.0-3.6v 8-pin ?green?/rohs soic, tape & reel

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